Showing 1 - 2 results of 2 for search '400179 Fadzlan Mohamad', query time: 0.02s Refine Results
  1. 1
    VLSI design of 8X8 BIT unsigned parallel multiplier using L. Dadda reduction tree method /

    VLSI design of 8X8 BIT unsigned parallel multiplier using L. Dadda reduction tree method / by 400179 Fadzlan Mohamad, Fakulti Kejuruteraan Elektrik

    Published 2004
  2. 2
    VLSI design of 8X8 BIT unsigned parallel multiplier using L.DADDA reduction tree method [electronic resource /

    VLSI design of 8X8 BIT unsigned parallel multiplier using L.DADDA reduction tree method [electronic resource / by 400179 Fadzlan Mohamad, Fakulti Kejuruteraan Elektrik

    Published 2004

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