Anant Agarwal

Agarwal in 2015 Anant Agarwal is an Indian computer architecture researcher. He is a professor of Electrical Engineering and Computer Science at the Massachusetts Institute of Technology (MIT), where he led the development of Alewife, an early cache coherent multiprocessor, and also has served as director of the MIT Computer Science and Artificial Intelligence Laboratory. He is the founder and CTO of Tilera, a fabless semiconductor company focusing on scalable multicore embedded processor design. He also serves as the CEO of edX, a joint partnership between MIT and Harvard University that offers free online learning. Provided by Wikipedia
Showing 1 - 20 results of 86 for search 'Anant Agarwal.', query time: 0.03s Refine Results
  1. 1
    Should planning of cervical pedicle screws be race specific? Computed tomography–based morphometric analysis

    Should planning of cervical pedicle screws be race specific? Computed tomography–based morphometric analysis by Ashish Agarwal, Anant Agarwal, Ashutosh Kumar

    Published 2023-01-01
    Get full text
    Article
  2. 2
    parallel communication mechanisms for sparse, irregular applications

    parallel communication mechanisms for sparse, irregular applications by Chong, Frederic T. (Frederic Tsyh-An)

    Published 2005
    Other Authors: “…Anant Agarwal.…”
    Get full text
    Thesis
  3. 3
    An implementation of the virtual wires interconnect scheme

    An implementation of the virtual wires interconnect scheme by Dahl, Matthew Lyle

    Published 2005
    Other Authors: “…Anant Agarwal.…”
    Get full text
    Thesis
  4. 4
    InnerView hardware debugger : a logic analysis tool for the Virtual Wires emulation system

    InnerView hardware debugger : a logic analysis tool for the Virtual Wires emulation system by Hanono, Silvina Zimi

    Published 2005
    Other Authors: “…Anant Agarwal.…”
    Get full text
    Thesis
  5. 5
    The design of an efficient hardware subroutine protocol for FPGAs

    The design of an efficient hardware subroutine protocol for FPGAs by Bauer, Trevor Joseph

    Published 2005
    Other Authors: “…Anant Agarwal.…”
    Get full text
    Thesis
  6. 6
    Virtual wires--overcoming pin limitations in FPGA-based logic emulation

    Virtual wires--overcoming pin limitations in FPGA-based logic emulation by Babb, Jonathan William

    Published 2005
    Other Authors: “…Anant Agarwal.…”
    Get full text
    Thesis
  7. 7
    Sinew : a system for improving the efficiency of wireless networks

    Sinew : a system for improving the efficiency of wireless networks by Robertson, Hans, 1977-

    Published 2005
    Other Authors: “…Anant Agarwal.…”
    Get full text
    Thesis
  8. 8
    Spatial software pipelining on distributed architectures for sparse matrix codes

    Spatial software pipelining on distributed architectures for sparse matrix codes by Duvall, Michelle, 1981-

    Published 2005
    Other Authors: “…Anant Agarwal.…”
    Get full text
    Thesis
  9. 9
    A shared-memory multiprocessor system using the raw tiled architecture

    A shared-memory multiprocessor system using the raw tiled architecture by Jakab, Levente, 1981-

    Published 2005
    Other Authors: “…Anant Agarwal.…”
    Get full text
    Thesis
  10. 10
    The design and implementation of a 3D graphics pipeline for the raw reconfigurable architecture

    The design and implementation of a 3D graphics pipeline for the raw reconfigurable architecture by Taylor, Kenneth William, 1980-

    Published 2005
    Other Authors: “…Anant Agarwal.…”
    Get full text
    Thesis
  11. 11
    Optimizing directory-based cache coherence on the RAW architecture

    Optimizing directory-based cache coherence on the RAW architecture by Ramaswamy, Satish

    Published 2006
    Other Authors: “…Anant Agarwal.…”
    Get full text
    Thesis
  12. 12
    A Raw processor interface to an 802.11b/g RF front end

    A Raw processor interface to an 802.11b/g RF front end by Walker, Benjamin Philip Eugene Zaks

    Published 2006
    Other Authors: “…Anant Agarwal.…”
    Get full text
    Thesis
  13. 13
    Mechanisms and interfaces for software-extended coherent shared memory

    Mechanisms and interfaces for software-extended coherent shared memory by Chaiken, David Lars

    Published 2006
    Other Authors: “…Anant Agarwal.…”
    Get full text
    Thesis
  14. 14
    The Alewife secondary storage subsystem

    The Alewife secondary storage subsystem by Chan, Wilson John

    Published 2006
    Other Authors: “…Anant Agarwal.…”
    Get full text
    Thesis
  15. 15
    Reptile : a distributed ILP compiler

    Reptile : a distributed ILP compiler by Bratt, Ian (Ian R.)

    Published 2006
    Other Authors: “…Anant Agarwal.…”
    Get full text
    Thesis
  16. 16
    Improving the performance of sparse cholesky factorization with fine grain synchronization

    Improving the performance of sparse cholesky factorization with fine grain synchronization by Tuteja, Manish Kumar

    Published 2007
    Other Authors: “…Anant Agarwal.…”
    Get full text
    Thesis
  17. 17
    MPEG encoding on the Raw microprocessor

    MPEG encoding on the Raw microprocessor by DeAngelis, Douglas J. (Douglas John)

    Published 2007
    Other Authors: “…Anant Agarwal.…”
    Get full text
    Thesis
  18. 18
    rMPI : an MPI-compliant message passing library for tiled architectures

    rMPI : an MPI-compliant message passing library for tiled architectures by Psota, James Ryan

    Published 2007
    Other Authors: “…Anant Agarwal.…”
    Get full text
    Thesis
  19. 19
    Reactive synchronization algorithms for multiprocessors

    Reactive synchronization algorithms for multiprocessors by Lim, Beng-Hong

    Published 2007
    Other Authors: “…Anant Agarwal.…”
    Get full text
    Thesis
  20. 20
    Multipass communication systems for tiled processor architectures

    Multipass communication systems for tiled processor architectures by Shnidman, Nathan R. (Nathan Robert)

    Published 2007
    Other Authors: “…Anant Agarwal.…”
    Get full text
    Thesis

Search Tools: