Anant Agarwal

Agarwal in 2015 Anant Agarwal is an Indian computer architecture researcher. He is a professor of electrical engineering and computer science at the Massachusetts Institute of Technology (MIT), where he led the development of Alewife, an early cache coherent multiprocessor, and has been director of the MIT Computer Science and Artificial Intelligence Laboratory. He is the founder and CTO of Tilera, a fabless semiconductor company focusing on scalable multicore embedded processor design. He is the CEO of edX, a joint partnership between MIT and Harvard University that offers free online learning. Provided by Wikipedia
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  1. 1
    Should planning of cervical pedicle screws be race specific? Computed tomography–based morphometric analysis

    Should planning of cervical pedicle screws be race specific? Computed tomography–based morphometric analysis by Ashish Agarwal, Anant Agarwal, Ashutosh Kumar

    Published 2023-01-01
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  2. 2
    Multiple giant pancreatic pseudocysts, a rare complication of acute pancreatitis – A case report

    Multiple giant pancreatic pseudocysts, a rare complication of acute pancreatitis – A case report by Albail Singh Yadav, Anant Agarwal, Ayush Maurya, Gaurang Agarwal

    Published 2024-10-01
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  3. 3
    Widening Access to Applied Machine Learning with TinyML

    Widening Access to Applied Machine Learning with TinyML by Vijay Janapa Reddi, Brian Plancher, Susan Kennedy, Laurence Moroney, Pete Warden, Lara Suzuki, Anant Agarwal, Colby Banbury, Massimo Banzi, Matthew Bennett, Benjamin Brown, Sharad Chitlangia, Radhika Ghosal, Sarah Grafman, Rupert Jaeger, Srivatsan Krishnan, Maximilian Lam, Daniel Leiker, Cara Mann, Mark Mazumder, Dominic Pajak, Dhilan Ramaprasad, J. Evan Smith, Matthew Stewart, Dustin Tingley

    Published 2022-01-01
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  4. 4
    parallel communication mechanisms for sparse, irregular applications

    parallel communication mechanisms for sparse, irregular applications by Chong, Frederic T. (Frederic Tsyh-An)

    Published 2005
    Other Authors: “…Anant Agarwal.…”
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    Thesis
  5. 5
    An implementation of the virtual wires interconnect scheme

    An implementation of the virtual wires interconnect scheme by Dahl, Matthew Lyle

    Published 2005
    Other Authors: “…Anant Agarwal.…”
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    Thesis
  6. 6
    InnerView hardware debugger : a logic analysis tool for the Virtual Wires emulation system

    InnerView hardware debugger : a logic analysis tool for the Virtual Wires emulation system by Hanono, Silvina Zimi

    Published 2005
    Other Authors: “…Anant Agarwal.…”
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    Thesis
  7. 7
    The design of an efficient hardware subroutine protocol for FPGAs

    The design of an efficient hardware subroutine protocol for FPGAs by Bauer, Trevor Joseph

    Published 2005
    Other Authors: “…Anant Agarwal.…”
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    Thesis
  8. 8
    Virtual wires--overcoming pin limitations in FPGA-based logic emulation

    Virtual wires--overcoming pin limitations in FPGA-based logic emulation by Babb, Jonathan William

    Published 2005
    Other Authors: “…Anant Agarwal.…”
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    Thesis
  9. 9
    Sinew : a system for improving the efficiency of wireless networks

    Sinew : a system for improving the efficiency of wireless networks by Robertson, Hans, 1977-

    Published 2005
    Other Authors: “…Anant Agarwal.…”
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    Thesis
  10. 10
    Spatial software pipelining on distributed architectures for sparse matrix codes

    Spatial software pipelining on distributed architectures for sparse matrix codes by Duvall, Michelle, 1981-

    Published 2005
    Other Authors: “…Anant Agarwal.…”
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    Thesis
  11. 11
    A shared-memory multiprocessor system using the raw tiled architecture

    A shared-memory multiprocessor system using the raw tiled architecture by Jakab, Levente, 1981-

    Published 2005
    Other Authors: “…Anant Agarwal.…”
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    Thesis
  12. 12
    The design and implementation of a 3D graphics pipeline for the raw reconfigurable architecture

    The design and implementation of a 3D graphics pipeline for the raw reconfigurable architecture by Taylor, Kenneth William, 1980-

    Published 2005
    Other Authors: “…Anant Agarwal.…”
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    Thesis
  13. 13
    Optimizing directory-based cache coherence on the RAW architecture

    Optimizing directory-based cache coherence on the RAW architecture by Ramaswamy, Satish

    Published 2006
    Other Authors: “…Anant Agarwal.…”
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    Thesis
  14. 14
    A Raw processor interface to an 802.11b/g RF front end

    A Raw processor interface to an 802.11b/g RF front end by Walker, Benjamin Philip Eugene Zaks

    Published 2006
    Other Authors: “…Anant Agarwal.…”
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    Thesis
  15. 15
    Mechanisms and interfaces for software-extended coherent shared memory

    Mechanisms and interfaces for software-extended coherent shared memory by Chaiken, David Lars

    Published 2006
    Other Authors: “…Anant Agarwal.…”
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    Thesis
  16. 16
    The Alewife secondary storage subsystem

    The Alewife secondary storage subsystem by Chan, Wilson John

    Published 2006
    Other Authors: “…Anant Agarwal.…”
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    Thesis
  17. 17
    Reptile : a distributed ILP compiler

    Reptile : a distributed ILP compiler by Bratt, Ian (Ian R.)

    Published 2006
    Other Authors: “…Anant Agarwal.…”
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    Thesis
  18. 18
    Improving the performance of sparse cholesky factorization with fine grain synchronization

    Improving the performance of sparse cholesky factorization with fine grain synchronization by Tuteja, Manish Kumar

    Published 2007
    Other Authors: “…Anant Agarwal.…”
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    Thesis
  19. 19
    MPEG encoding on the Raw microprocessor

    MPEG encoding on the Raw microprocessor by DeAngelis, Douglas J. (Douglas John)

    Published 2007
    Other Authors: “…Anant Agarwal.…”
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    Thesis
  20. 20
    rMPI : an MPI-compliant message passing library for tiled architectures

    rMPI : an MPI-compliant message passing library for tiled architectures by Psota, James Ryan

    Published 2007
    Other Authors: “…Anant Agarwal.…”
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    Thesis

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