Showing 1 - 20 results of 161 for search 'Boon, Chirn Chye', query time: 0.07s Refine Results
  1. 1
    Novel techniques for fully-intergrated RF CMOS phase-locked loop frequency synthesizer

    Novel techniques for fully-intergrated RF CMOS phase-locked loop frequency synthesizer by Boon, Chirn Chye.

    Published 2008
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    Thesis
  2. 2
    An in-phase-coupled class-C quadrature VCO with tunable phase error

    An in-phase-coupled class-C quadrature VCO with tunable phase error by Zhang, Yuxiang, Boon, Chirn Chye

    Published 2015
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    Journal Article
  3. 3
    A 40 GHz CMOS PLL with -75-dBc reference spur and 121.9-fs rms jitter featuring a quadrature sampling phase-frequency detector

    A 40 GHz CMOS PLL with -75-dBc reference spur and 121.9-fs rms jitter featuring a quadrature sampling phase-frequency detector by Liang, Yuan, Boon, Chirn Chye

    Published 2022
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    Journal Article
  4. 4
    Cell-based variable-gain amplifiers with accurate dB-linear characteristic in 0.18 µm CMOS technology

    Cell-based variable-gain amplifiers with accurate dB-linear characteristic in 0.18 µm CMOS technology by Liu, Hang, Zhu, Xi, Boon, Chirn Chye

    Published 2015
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    Journal Article
  5. 5
    A 0.013-mm2 0.53-mW/Gb/s 32-Gb/s hybrid analog equalizer under 21-dB channel loss in 65-nm CMOS

    A 0.013-mm2 0.53-mW/Gb/s 32-Gb/s hybrid analog equalizer under 21-dB channel loss in 65-nm CMOS by Balachandran, Arya, Chen, Yong, Boon, Chirn Chye

    Published 2020
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    Journal Article
  6. 6
    A 40 GHz on-chip power combine load for mm-wave power amplifier

    A 40 GHz on-chip power combine load for mm-wave power amplifier by Lin, Jiafu, Zhang, Gary, Boon, Chirn Chye

    Published 2020
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    Journal Article
  7. 7
    A 23.4 mW -72-dBc reference spur 40 GHz CMOS PLL featuring a spur-compensation phase detector

    A 23.4 mW -72-dBc reference spur 40 GHz CMOS PLL featuring a spur-compensation phase detector by Liang, Yuan, Boon, Chirn Chye, Chen, Qian

    Published 2022
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    Journal Article
  8. 8
    A 0.6 V 4 GS/s - 56.4 dB THD voltage-to-time converter in 28 nm CMOS

    A 0.6 V 4 GS/s - 56.4 dB THD voltage-to-time converter in 28 nm CMOS by Chen, Qian, Boon, Chirn Chye, Liang, Yuan

    Published 2023
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    Journal Article
  9. 9
    A 20.2–57.1 GHz Inductor-less Divide-by-4 Divider Chain

    A 20.2–57.1 GHz Inductor-less Divide-by-4 Divider Chain by Yi, Xiang, Liang, Zhipeng, Boon, Chirn Chye

    Published 2018
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    Conference Paper
  10. 10
    A 4.06 mW 10-bit 150 MS/s SAR ADC with 1.5-bit/cycle operation for medical imaging applications

    A 4.06 mW 10-bit 150 MS/s SAR ADC with 1.5-bit/cycle operation for medical imaging applications by Sunny, Sharma, Chen, Yong, Boon, Chirn Chye

    Published 2019
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    Journal Article
  11. 11
    0.058 mm2 13 Gbit/s inductorless analogue equaliser with low-frequency equalisation compensating 15 dB channel loss

    0.058 mm2 13 Gbit/s inductorless analogue equaliser with low-frequency equalisation compensating 15 dB channel loss by Boon, Chirn Chye, Balachandran, Arya, Chen, Yong, Choi, Pilsoon

    Published 2019
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    Journal Article
  12. 12
    A 3GS/s highly linear energy efficient constant-slope based voltage-to-time converter

    A 3GS/s highly linear energy efficient constant-slope based voltage-to-time converter by Chen, Qian, Liang, Yuan, Kim, Bongjin, Boon, Chirn Chye

    Published 2020
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    Conference Paper
  13. 13
    A 20-80 MHz continuously tunable Gm-C low-pass filter for ultra-low power WBAN receiver front-end

    A 20-80 MHz continuously tunable Gm-C low-pass filter for ultra-low power WBAN receiver front-end by Wang, Xiaoying, Boon, Chirn Chye, Yang, Kaituo, Kong, Lingshan

    Published 2022
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    Journal Article
  14. 14
    17.8 A single-channel 10GS/s 8b>36.4d8 SNDR time-domain ADC featuring loop-unrolled asynchronous successive approximation in 28nm CMOS

    17.8 A single-channel 10GS/s 8b>36.4d8 SNDR time-domain ADC featuring loop-unrolled asynchronous successive approximation in 28nm CMOS by Chen, Qian, Liang, Yuan, Boon, Chirn Chye, Liu, Qing

    Published 2023
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    Conference Paper
  15. 15
    A single-channel voltage-scalable 8-GS/s 8-b > 37.5-dB SNDR time-domain ADC with asynchronous pipeline successive approximation in 28-nm CMOS

    A single-channel voltage-scalable 8-GS/s 8-b > 37.5-dB SNDR time-domain ADC with asynchronous pipeline successive approximation in 28-nm CMOS by Chen, Qian, Boon, Chirn Chye, Liu, Qing, Liang, Yuan

    Published 2023
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    Journal Article
  16. 16
    A dual-path subsampling PLL with ring VCO phase noise suppression

    A dual-path subsampling PLL with ring VCO phase noise suppression by Dong, Yangtao, Boon, Chirn Chye, Liu, Zhe, Yang, Kaituo

    Published 2023
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    Journal Article
  17. 17
    A 2.6–3.4 ghz fractional-N sub-sampling phase-locked loop using a calibration-free phase-switching-sub-sampling technique

    A 2.6–3.4 ghz fractional-N sub-sampling phase-locked loop using a calibration-free phase-switching-sub-sampling technique by Liang, Zhipeng, Yi, Xiang, Yang, Kaituo, Boon, Chirn Chye

    Published 2019
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    Journal Article
  18. 18
    A W-band switch-less Dicke receiver for millimeter-wave imaging in 65nm CMOS

    A W-band switch-less Dicke receiver for millimeter-wave imaging in 65nm CMOS by Feng, Guangyin, Yi, Xiang, Meng, Fanyi, Boon, Chirn Chye

    Published 2018
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    Journal Article
  19. 19
    A low-noise amplifier with continuously-tuned input matching frequency and output resonance frequency

    A low-noise amplifier with continuously-tuned input matching frequency and output resonance frequency by Zhu, Xi, Boon, Chirn Chye, Iji, Ayobami, Sun, Yichuang, Heimlich, Michael

    Published 2013
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    Conference Paper
  20. 20
    A 0.6-V high reverse-isolation through feedback self-cancellation for single-stage noncascode CMOS LNA

    A 0.6-V high reverse-isolation through feedback self-cancellation for single-stage noncascode CMOS LNA by Tran, T. T. N., Boon, Chirn Chye, Do, Manh Anh, Yeo, Kiat Seng

    Published 2013
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    Journal Article

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