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CYRIL PRASANNA RAJ
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CYRIL PRASANNA RAJ
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1
PQ data compression algorithm with modified quantizer and adaptive band logic using DTCWT
by
EKANTHAIAH PRATHIBHA
,
ASHWATHNARAYAN MANJUNATHA
,
CYRIL PRASANNA RAJ
Published 2018-03-01
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2
Memory Efficient High Speed Systolic Array Architecture Design with Multiplexed Distributed Arithmetic for 2D DTCWT Computation on FPGA
by
Poornima B.
,
Sumathi A.
,
Cyril Prasanna Raj
P
Published 2019-12-01
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Article
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