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1
Robust and Energy-Efficient Ultra-Low-Voltage Circuit Design under Timing Constraints in 65/45 nm CMOS by David Bol
Published 2011-01-01
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Study of Back Biasing Schemes for ULV Logic from the Gate Level to the IP Level by Guerric de Streel, David Bol
Published 2014-07-01
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A Sub-mW Cortex-M4 Microcontroller Design for IoT Software-Defined Radios by Mathieu Xhonneux, Jerome Louveaux, David Bol
Published 2023-01-01
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Enhancing the Reliability of Dense LoRaWAN Networks With Multi-User Receivers by Joachim Tapparel, Mathieu Xhonneux, David Bol, Jerome Louveaux, Andreas Burg
Published 2021-01-01
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