Alleviation of Negative-Bias Temperature Instability in Si p-FinFETs With ALD W Gate-Filling Metal by Annealing Process Optimization by Longda Zhou, Qianqian Liu, Hong Yang, Zhigang Ji, Hao Xu, Guilei Wang, Eddy Simoen, Haojie Jiang, Ying Luo, Zhenzhen Kong, Guobin Bai, Jun Luo, Huaxiang Yin, Chao Zhao, Wenwu Wang

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