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    Array-Specific Dataflow Caches for High-Level Synthesis of Memory-Intensive Algorithms on FPGAs

    Array-Specific Dataflow Caches for High-Level Synthesis of Memory-Intensive Algorithms on FPGAs by Giovanni Brignone, M. Usman Jamal, Mihai T. Lazarescu, Luciano Lavagno

    Published 2022-01-01
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