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  1. 1
    Accelerated and Highly Correlated ASIC Synthesis of AI Hardware Subsystems Using CGP

    Accelerated and Highly Correlated ASIC Synthesis of AI Hardware Subsystems Using CGP by H. C. Prashanth, Madhav Rao

    Published 2024-01-01
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  2. 2
    Correction: Trainable windows for SincNet architecture

    Correction: Trainable windows for SincNet architecture by H. C. Prashanth, Madhav Rao, Dhanya Eledath, V. Ramasubramanian

    Published 2023-02-01
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