Showing 1 - 3 results of 3 for search 'HOO, C.-S.', query time: 0.03s
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Cost reduction in bottom-up hierarchical-based VLSI floorplanning designs by Hoo, C.S., Kanesan, J., Ramiah, H.
Published 2015Article -
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Ant System-Corner Insertion Sequence: An Efficient VLSI Hard Module Placer by HOO, C.-S., JEEVAN, K., GANAPATHY, V., RAMIAH, H.
Published 2013-02-01
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