Design of a sub-picosecond jitter with adjustable-range CMOS delay-locked loop for high-speed and low-power applications by Abdulrazzaq, Bilal Isam, Ibrahim, Omar J., Kawahito, Shoji, Mohd Sidek, Roslina, Shafie, Suhaidi, Md Yunus, Nurul Amziah, Lee, Lini, Abdul Halin, Izhal

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