Sub-20 nm multilayer nanopillar patterning for hybrid SET/CMOS integration by M.-L. Pourteau, A. Gharbi, P. Brianceau, J.-A. Dallery, F. Laulagnet, G. Rademaker, R. Tiron, H.-J. Engelmann, J. von Borany, K.-H. Heinig, M. Rommel, L. Baier

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