Evaluation of various phase-transition materials for steep switching super-low power application in the latest technology node by Hanggyo Jung, Jeesoo Chang, Jongwook Jeon

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Device and Circuit Exploration of Multi-Nanosheet Transistor for Sub-3 nm Technology Node by Yoongeun Seon, Jeesoo Chang, Changhyun Yoo, Jongwook Jeon

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Optimization of Gate-All-Around Device to Achieve High Performance and Low Power with Low Substrate Leakage by Changhyun Yoo, Jeesoo Chang, Sugil Park, Hyungyeong Kim, Jongwook Jeon

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Investigation on the Effects of Interconnect RC in 3nm Technology Node Using Path-Finding Process Design Kit by Yeji Lee, Wonyeong Jang, Kyungbae Kwon, Jihun Park, Changhyun Yoo, Jeesoo Chang, Jongwook Jeon

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Hyper-FET’s Phase-Transition-Materials Design Guidelines for Ultra-Low Power Applications at 3 nm Technology Node by Hanggyo Jung, Jeesoo Chang, Changhyun Yoo, Jooyoung Oh, Sumin Choi, Juyeong Song, Jongwook Jeon

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3D AND-Type Stacked Array for Neuromorphic Systems by Taejin Jang, Suhyeon Kim, Jeesoo Chang, Kyung Kyu Min, Sungmin Hwang, Kyungchul Park, Jong-Ho Lee, Byung-Gook Park

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A Systematic Compact Model Parameter Calibration with Adaptive Pattern Search Algorithm by Jeesoo Chang, Sungmin Hwang, Kyungchul Park, Taejin Jang, Kyung-Kyu Min, Min-Hye Oh, Jonghyuk Park, Jong-Ho Lee, Byung-Gook Park

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Low-Latency Spiking Neural Networks Using Pre-Charged Membrane Potential and Delayed Evaluation by Sungmin Hwang, Jeesoo Chang, Min-Hye Oh, Kyung Kyu Min, Taejin Jang, Kyungchul Park, Junsu Yu, Jong-Ho Lee, Byung-Gook Park

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