Showing 1 - 11 results of 11 for search 'Jinsu Jeong', query time: 0.03s Refine Results
  1. 1
    Analysis of TSV-Induced Mechanical Stress and Electrical Noise Coupling in Sub 5-nm Node Nanosheet FETs for Heterogeneous 3D-ICs

    Analysis of TSV-Induced Mechanical Stress and Electrical Noise Coupling in Sub 5-nm Node Nanosheet FETs for Heterogeneous 3D-ICs by Jinsu Jeong, Jun-Sik Yoon, Rock-Hyun Baek

    Published 2021-01-01
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  2. 2
    Punch-Through-Stopper Free Nanosheet FETs With Crescent Inner-Spacer and Isolated Source/Drain

    Punch-Through-Stopper Free Nanosheet FETs With Crescent Inner-Spacer and Isolated Source/Drain by Jun-Sik Yoon, Jinsu Jeong, Seunghwan Lee, Rock-Hyun Baek

    Published 2019-01-01
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  3. 3
    Systematic DC/AC Performance Benchmarking of Sub-7-nm Node FinFETs and Nanosheet FETs

    Systematic DC/AC Performance Benchmarking of Sub-7-nm Node FinFETs and Nanosheet FETs by Jun-Sik Yoon, Jinsu Jeong, Seunghwan Lee, Rock-Hyun Baek

    Published 2018-01-01
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  4. 4
    Bottom Oxide Bulk FinFETs Without Punch-Through-Stopper for Extending Toward 5-nm Node

    Bottom Oxide Bulk FinFETs Without Punch-Through-Stopper for Extending Toward 5-nm Node by Jun-Sik Yoon, Jinsu Jeong, Seunghwan Lee, Rock-Hyun Baek

    Published 2019-01-01
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  5. 5
    Comprehensive Analysis of Source and Drain Recess Depth Variations on Silicon Nanosheet FETs for Sub 5-nm Node SoC Application

    Comprehensive Analysis of Source and Drain Recess Depth Variations on Silicon Nanosheet FETs for Sub 5-nm Node SoC Application by Jinsu Jeong, Jun-Sik Yoon, Seunghwan Lee, Rock-Hyun Baek

    Published 2020-01-01
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  6. 6
    Monolithic 3D 6T-SRAM Based on Newly Designed Gate and Source/Drain Bottom Contact Schemes

    Monolithic 3D 6T-SRAM Based on Newly Designed Gate and Source/Drain Bottom Contact Schemes by Junjong Lee, Jun-Sik Yoon, Jinsu Jeong, Seunghwan Lee, Sanguk Lee, Rock-Hyun Baek

    Published 2021-01-01
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  7. 7
    Neural Compact Modeling Framework for Flexible Model Parameter Selection with High Accuracy and Fast SPICE Simulation

    Neural Compact Modeling Framework for Flexible Model Parameter Selection with High Accuracy and Fast SPICE Simulation by Seungjoon Eom, Hyeok Yun, Hyundong Jang, Kyeongrae Cho, Seunghwan Lee, Jinsu Jeong, Rock‐Hyun Baek

    Published 2024-04-01
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  8. 8
    Source/Drain Patterning FinFETs as Solution for Physical Area Scaling Toward 5-nm Node

    Source/Drain Patterning FinFETs as Solution for Physical Area Scaling Toward 5-nm Node by Jun-Sik Yoon, Seunghwan Lee, Junjong Lee, Jinsu Jeong, Hyeok Yun, Bohyeon Kang, Rock-Hyun Baek

    Published 2019-01-01
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  9. 9
    Sensitivity of Inner Spacer Thickness Variations for Sub-3-nm Node Silicon Nanosheet Field-Effect Transistors

    Sensitivity of Inner Spacer Thickness Variations for Sub-3-nm Node Silicon Nanosheet Field-Effect Transistors by Sanguk Lee, Jinsu Jeong, Jun-Sik Yoon, Seunghwan Lee, Junjong Lee, Jaewan Lim, Rock-Hyun Baek

    Published 2022-09-01
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  10. 10
    A Novel Source/Drain Extension Scheme with Laser-Spike Annealing for Nanosheet Field-Effect Transistors in 3D ICs

    A Novel Source/Drain Extension Scheme with Laser-Spike Annealing for Nanosheet Field-Effect Transistors in 3D ICs by Sanguk Lee, Jinsu Jeong, Bohyeon Kang, Seunghwan Lee, Junjong Lee, Jaewan Lim, Hyeonjun Hwang, Sungmin Ahn, Rockhyun Baek

    Published 2023-02-01
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  11. 11
    Novel Modeling Approach to Analyze Threshold Voltage Variability in Short Gate-Length (15–22 nm) Nanowire FETs with Various Channel Diameters

    Novel Modeling Approach to Analyze Threshold Voltage Variability in Short Gate-Length (15–22 nm) Nanowire FETs with Various Channel Diameters by Seunghwan Lee, Jun-Sik Yoon, Junjong Lee, Jinsu Jeong, Hyeok Yun, Jaewan Lim, Sanguk Lee, Rock-Hyun Baek

    Published 2022-05-01
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