Joel Emer
Joel S. Emer (born March 2, 1954) is a pioneer in computer performance analysis techniques and a microprocessor architect. He is currently a researcher at Nvidia, and a Professor of the Practice at MIT, and was formerly an Intel Fellow. He was the 2009 recipient of the Eckert–Mauchly Award. Provided by Wikipedia
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Freely scalable and reconfigurable optical hardware for deep learning by Liane Bernstein, Alexander Sludds, Ryan Hamerly, Vivienne Sze, Joel Emer, Dirk Englund
Published 2021-02-01
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HAsim : cycle-accurate multicore performance models on FPGAs by Pellauer, Michael (Michael Ignatius)
Published 2011Other Authors: “…Arvind and Joel Emer.…”
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Functional and timing models for a programmable hardware accelerator by Fox, Matthew (Matthew M.)
Published 2016Other Authors: “…Joel Emer and Vivienne Sze.…”
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Automatic application-specific optimizations under FPGA memory abstractions by Yang, Hsin-Jung
Published 2017Other Authors: “…Srinivas Devadas and Joel Emer.…”
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Architecture design for highly flexible and energy-efficient deep neural network accelerators by Chen, Yu-Hsin, Ph. D. Massachusetts Institute of Technology
Published 2018Other Authors: “…Vivienne Sze and Joel Emer.…”
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