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    40 Gbit/s on-off-keyed system with 5.71 GHz clock recovery circuit using duty cycle division multiplexing

    40 Gbit/s on-off-keyed system with 5.71 GHz clock recovery circuit using duty cycle division multiplexing by Amouzad Mahdiraji, G., Malekmohammadi, A., Fauzi Abas, A., Khazani Abdullah, M.

    Published 2009
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    Conference or Workshop Item

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