Krste Asanović
Krste Asanović is an engineering academic from the University of California, Berkeley. He has written and co-authored many academic papers concerning computer architecture. , he is chairman of the Board of the RISC-V Foundation.Asanović was named Fellow of the Institute of Electrical and Electronics Engineers (IEEE) in 2014 ''for contributions to computer architecture''. He was elected as an ACM Fellow in 2018 for "contributions to computer architecture, including the open RISC-V instruction set and Agile hardware".
Asanović received a PhD in computer science from Berkeley in 1998 under John Wawrzynek. In 2015, along with RISC-V researchers he co-founded SiFive, a fabless semiconductor company and provider of commercial RISC-V processor IP, where he serves as its chief architect. Provided by Wikipedia
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1
EProf : an energy profiler for the iPAQ by Koskelin, Kelly, 1980-
Published 2005Other Authors: “…Krste Asanovic.…”
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Hardware support for unbounded transactional memory by Lie, Sean, 1980-
Published 2005Other Authors: “…Krste Asanovic.…”
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Video over IP : an example reconfigurable computing application for a handheld device by Kamenetskaya, Elina, 1980-
Published 2006Other Authors: “…Krste Asanovic.…”
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RingScalar: A Complexity-Effective Out-of-Order Superscalar Microarchitecture by Tseng, Jessica H., Asanovic, Krste
Published 2006Other Authors: “…Krste Asanovic…”
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The Extreme Benchmark Suite : measuring high-performance embedded systems by Gerding, Steven (Steven Bradley)
Published 2006Other Authors: “…Krste Asanovic.…”
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Fast Fourier transform on a 3D FPGA by Basha, Elizabeth (Elizabeth Ann)
Published 2006Other Authors: “…Krste Asanovic.…”
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Scale Control Processor Test-Chip by Batten, Christopher, Krashinsky, Ronny, Asanovic, Krste
Published 2007Other Authors: “…Krste Asanovic…”
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Optimal digital system design in deep submicron technology by Heo, Seongmoo, 1977-
Published 2007Other Authors: “…Krste Asanović.…”
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Latency reduction techniques in chip multiprocessor cache systems by Zhang, Michael Ruogu, 1977-
Published 2007Other Authors: “…Krste Asanović.…”
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AXCIS : rapid processor architectural exploration using canonical instruction segments by Liu, Rose F. (Rose Frances)
Published 2007Other Authors: “…Krste Asanović.…”
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SCALE DRAM subsystem power analysis by Bhalodia, Vimal
Published 2007Other Authors: “…Krste Asanović.…”
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Banked microarchitectures for complexity-effective superscalar microprocessors by Tseng, Jessica Hui-Chun, 1977-
Published 2007Other Authors: “…Krste Asanović.…”
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Circuits for high-performance low-power VLSI logic by Ma, Albert
Published 2007Other Authors: “…Krste Asanović.…”
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Summarizing multiprocessor program execution with versatile, microarchitecture-independent snapshots by Barr, Kenneth C. (Kenneth Charles), 1978-
Published 2007Other Authors: “…Krste Asanović.…”
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Microprocessor energy characterization and optimization through fast, accurate, and flexible simulation by Krashinsky, Ronny (Ronny Meir), 1978-
Published 2007Other Authors: “…Krste Asanović.…”
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Vector-thread architecture and implementation by Krashinsky, Ronny (Ronny Meir), 1978-
Published 2009Other Authors: “…Krste Asanović.…”
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Emulation of microprocessor memory systems using the RAMP design framework by Khan, Asif I. (Asif Imtiaz)
Published 2008Other Authors: “…Krste Asanović.…”
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Reducing exception management overhead with software restart markers by Hampton, Mark Jerome, 1977-
Published 2008Other Authors: “…Krste Asanović.…”
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Simplified vector-thread architectures for flexible and efficient data-parallel accelerators by Batten, Christopher Francis
Published 2010Other Authors: “…Krste Asanović.…”
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Energy-efficient register file design by Tseng, Jessica Hui-Chun, 1977-
Published 2013Other Authors: “…Krste Asanović.…”
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