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    The mixed MCML/TG logic and design of ternary T gate and D-latch circuits(MCML/TG混合结构与三值T门和三值D-latch电路设计)

    The mixed MCML/TG logic and design of ternary T gate and D-latch circuits(MCML/TG混合结构与三值T门和三值D-latch电路设计) gan ZHANGZhuan(章专), LIANMing-chao(连明超)

    Cyhoeddwyd 2012-09-01
    Cael y testun llawn
    Erthygl

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