Hardware mechanism for redundancy restraint and the analysis of their working procedure(冗余抑制的硬件实现及作用过程分析) Tekijä WUXun-wei(吴训威), LUYang-jian(卢仰坚)

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Logic design of priority encoder by restraining redundancy(抑制冗余优先编码器的逻辑设计) Tekijä LUYang-jian(卢仰坚), WUXun-wei(吴训威)

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Behavior sequence and technique of generation based on multiple-valued logic(行为序列及基于多值逻辑的产生技术) Tekijä LUYang-jian(卢仰坚), WUXun-wei(吴训威)

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Research on multivalued pulse circuits based on Schmitt circuits(基于施密特电路的多值脉冲电路研究) Tekijä WANGPeng-jun(汪鹏君), HUJian-ping(胡建平), LUYang-jian(卢仰坚)

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Characteristics detection and generation of ternary sequences(三值序列的特征检测及其产生) Tekijä WUXun-wei(吴训威), LUYang-jian(卢仰坚), XIAYin-shui(夏银水)

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Low power serial magnitude comparator based on the Clock-Gating technique(基于门控技术的低功耗串行比较器) Tekijä LUYang-jian(卢仰坚), WUXun-wei(吴训威), WangPeng-jun(汪鹏君)

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