Instruction-Level Execution Migration by Devadas, Srinivas, Lis, Mieszko, Khan, Omer

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EM2: A Scalable Shared-Memory Multicore Architecture by Khan, Omer, Lis, Mieszko, Devadas, Srini

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Superscalar processors via automatic microarchitecture transformations by Lis, Mieszko N. (Mieszko Norbert), 1977-

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Hardware-level fine-grained thread migration by Lis, Mieszko N. (Mieszko Norbert), 1977-

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DCC: A Dependable Cache Coherence Multicore Architecture by Khan, Omer, Lis, Mieszko, Sinangil, Yildiz, Devadas, Srinivas

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Thread Migration Prediction for Distributed Shared Caches by Shim, Keun Sup, Lis, Mieszko, Khan, Omer, Devadas, Srinivas

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The Execution Migration Machine: Directoryless Shared-Memory Architecture by Shim, Keun Sup, Lis, Mieszko, Khan, Omer, Devadas, Srinivas

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Judicious Thread Migration When Accessing Distributed Shared Caches by Shim, Keun Sup, Lis, Mieszko, Khan, Omer, Devadas, Srinivas

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Guaranteed in-order packet delivery using Exclusive Dynamic Virtual Channel Allocation by Devadas, Srinivas, Cho, Myong Hyon, Shim, Keun Sup, Lis, Mieszko

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Path-diverse In-order Routing by Lis, Mieszko, Cho, Myong Hyon, Shim, Keun Sup, Devadas, Srinivas

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Efficient stochastic simulation of reaction-diffusion processes via direct compilation by Lis, Mieszko, Artyomov, Maxim N., Chakraborty, Arup K., Devadas, Srinivas

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Memory coherence in the age of multicores by Lis, Mieszko, Shim, Keun Sup, Cho, Myong Hyon, Devadas, Srinivas

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Scalable directoryless shared memory coherence using execution migration by Lis, Mieszko, Shim, Keun Sup, Cho, Myong Hyon, Khan, Omer, Devadas, Srinivas

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Library Cache Coherence by Shim, Keun Sup, Cho, Myong Hyon, Lis, Mieszko, Khan, Omer, Devadas, Srinivas

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Directoryless shared memory coherence using execution migration by Lis, Mieszko, Shim, Keun Sup, Cho, Myong Hyon, Khan, Omer, Devadas, Srinivas

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CD4 and CD8 binding to MHC molecules primarily acts to enhance Lck delivery by Davis, M. M., Artyomov, Maxim N., Lis, Mieszko, Chakraborty, Arup K, Devadas, Srinivas

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Path-Based, Randomized, Oblivious, Minimal Routing by Cho, Myong Hyon, Lis, Mieszko, Shim, Keun Sup, Kinsy, Michel A., Devadas, Srinivas

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ARCc: A case for an architecturally redundant cache-coherence architecture for large multicores by Khan, Omer, Hoffmann, Henry Christian, Lis, Mieszko, Hijaz, Farrukh, Agarwal, Anant, Devadas, Srinivas

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Design tradeoffs for simplicity and efficient verification in the Execution Migration Machine by Shim, Keun Sup, Lis, Mieszko, Cho, Myong Hyon, Devadas, Srinivas, Lebedev, Ilia A.

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Oblivious Routing in On-Chip Bandwidth-Adaptive Networks by Kinsy, Michel, Wen, Tina, Shim, Keun Sup, Lis, Mieszko, Cho, Myong Hyon, Devadas, Srinivas

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