Energy-efficient hardware accelerators based on bit-serial graph and memory-centric computing architectures af Mu, Junjie

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A scalable CMOS Ising computer featuring sparse and reconfigurable spin interconnects for solving combinatorial optimization problems af Su, Yuqi, Mu, Junjie, Kim, Hyunjoon, Kim, Bongjin

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A time-domain wavefront computing accelerator with a 32 × 32 reconfigurable PE array af Yu, Chengshuo, Mu, Junjie, Su, Yuqi, Chai, Kevin Tshun Chuan, Kim, Tony Tae-Hyoung, Kim, Bongjin

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