The design and implementation of a low-power gating scan element in 32/28 nm CMOS technology by Naeini, M. M., Dass, S. B., Ooi, C. Y.

An integrated DFT solution for power reduction in scan test applications by low power gating scan cell by Naeini, M. M., Dass, S. B., Ooi, C. Y., Yoneda, T., Inoue, M.

A review on reconfiguration of radial electrical distribution network through heuristic methods by Ferdavani , A. K., Mohd. Zin, Abdullah Asuhaimi, Khairuddin, Azhar, Naeini, M. M.