Showing 1 - 2 results of 2 for search 'Paraman, N.', query time: 0.02s Refine Results
  1. 1
    Test register insertion at RTL based on reduced BIST

    Test register insertion at RTL based on reduced BIST by Paraman, N., Ooi, C. Y., Sha'ameri, A. Z., Fujiwara, H.

    Published 2017
    Article
  2. 2
    Reliability of graphene as charge storage layer in floating gate flash memory

    Reliability of graphene as charge storage layer in floating gate flash memory by Ahmad, M. H., Alias, N. E., Hamzah, A., Johari, Z., Abidin, M. S. Z., Paraman, N., Ismail, R.

    Published 2019
    Article

Search Tools: