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Author
Park, Matthew
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Park, Matthew
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1
A 0.13[mu]m CMOS 78dB SNDR 87mW 20MHz BW CT [Delta Sigma] ADC with VCO-based integrator and quantizer
by
Park, Matthew
Published 2010
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2
A 4th order continuous-time [Delta] [Epsilon] ADC with VCO-based integrator and quantizer
by
Park, Matthew
Jeremiah
Published 2009
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Thesis
3
An optical-electrical sub-sampling down-conversion receiver with continuous-time [Sigma] [Delta] modulation
by
Park, Matthew
(Matthew J.)
Published 2006
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Thesis
4
A 78 dB SNDR 87 mW 20 MHz Bandwidth Continuous-Time Delta Sigma ADC With VCO-Based Integrator and Quantizer Implemented in 0.13 mu m CMOS
by
Park, Matthew
,
Perrott, Michael H.
Published 2010
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Article
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