A Novel Sub-5-nm Node Dual-Workfunction Folded Cascode Nanosheet FETs for Low Power Mobile Applications by Jun-Sik Yoon, Rock-Hyun Baek

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Analysis of TSV-Induced Mechanical Stress and Electrical Noise Coupling in Sub 5-nm Node Nanosheet FETs for Heterogeneous 3D-ICs by Jinsu Jeong, Jun-Sik Yoon, Rock-Hyun Baek

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Arbitrary Font Generation by Encoder Learning of Disentangled Features by Jeong-Sik Lee, Rock-Hyun Baek, Hyun-Chul Choi

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Punch-Through-Stopper Free Nanosheet FETs With Crescent Inner-Spacer and Isolated Source/Drain by Jun-Sik Yoon, Jinsu Jeong, Seunghwan Lee, Rock-Hyun Baek

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Systematic DC/AC Performance Benchmarking of Sub-7-nm Node FinFETs and Nanosheet FETs by Jun-Sik Yoon, Jinsu Jeong, Seunghwan Lee, Rock-Hyun Baek

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Digital/Analog Performance Optimization of Vertical Nanowire FETs Using Machine Learning by Jun-Sik Yoon, Seunghwan Lee, Hyeok Yun, Rock-Hyun Baek

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Bottom Oxide Bulk FinFETs Without Punch-Through-Stopper for Extending Toward 5-nm Node by Jun-Sik Yoon, Jinsu Jeong, Seunghwan Lee, Rock-Hyun Baek

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Comprehensive Analysis of Source and Drain Recess Depth Variations on Silicon Nanosheet FETs for Sub 5-nm Node SoC Application by Jinsu Jeong, Jun-Sik Yoon, Seunghwan Lee, Rock-Hyun Baek

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Neural Approach for Modeling and Optimizing Si-MOSFET Manufacturing by Hyun-Chul Choi, Hyeok Yun, Jun-Sik Yoon, Rock-Hyun Baek

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Investigation of Program Efficiency Overshoot in 3D Vertical Channel NAND Flash with Randomly Distributed Traps by Chanyang Park, Jun-Sik Yoon, Kihoon Nam, Hyundong Jang, Minsang Park, Rock-Hyun Baek

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Monolithic 3D 6T-SRAM Based on Newly Designed Gate and Source/Drain Bottom Contact Schemes by Junjong Lee, Jun-Sik Yoon, Jinsu Jeong, Seunghwan Lee, Sanguk Lee, Rock-Hyun Baek

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Neural Compact Modeling Framework for Flexible Model Parameter Selection with High Accuracy and Fast SPICE Simulation by Seungjoon Eom, Hyeok Yun, Hyundong Jang, Kyeongrae Cho, Seunghwan Lee, Jinsu Jeong, Rock‐Hyun Baek

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Cryogenic Body Bias Effect in DRAM Peripheral and Buried-Channel-Array Transistor for Quantum Computing Applications by Hyunseo You, Kihoon Nam, Jehyun An, Chanyang Park, Donghyun Kim, Seonhaeng Lee, Namhyun Lee, Rock-Hyun Baek

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Source/Drain Patterning FinFETs as Solution for Physical Area Scaling Toward 5-nm Node by Jun-Sik Yoon, Seunghwan Lee, Junjong Lee, Jinsu Jeong, Hyeok Yun, Bohyeon Kang, Rock-Hyun Baek

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Sensitivity of Inner Spacer Thickness Variations for Sub-3-nm Node Silicon Nanosheet Field-Effect Transistors by Sanguk Lee, Jinsu Jeong, Jun-Sik Yoon, Seunghwan Lee, Junjong Lee, Jaewan Lim, Rock-Hyun Baek

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A Review of Multi-Modal Learning from the Text-Guided Visual Processing Viewpoint by Ubaid Ullah, Jeong-Sik Lee, Chang-Hyeon An, Hyeonjin Lee, Su-Yeong Park, Rock-Hyun Baek, Hyun-Chul Choi

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Novel Modeling Approach to Analyze Threshold Voltage Variability in Short Gate-Length (15–22 nm) Nanowire FETs with Various Channel Diameters by Seunghwan Lee, Jun-Sik Yoon, Junjong Lee, Jinsu Jeong, Hyeok Yun, Jaewan Lim, Sanguk Lee, Rock-Hyun Baek

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Curing Process on Passivation Layer for Backside-Illuminated CMOS Image Sensor Application by Jongseo Park, Kyeong-Keun Choi, Jehyun An, Bohyeon Kang, Hyeonseo You, Giryun Hong, Sung-Min Ahn, Rock-Hyun Baek

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Extraction of Device Structural Parameters Through DC/AC Performance Using an MLP Neural Network Algorithm by Hyundong Jang, Hyeok Yun, Chanyang Park, Kyeongrae Cho, Kihoon Nam, Jun-Sik Yoon, Hyun-Chul Choi, Rock-Hyun Baek

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Holistic Optimization of Trap Distribution for Performance/Reliability in 3-D NAND Flash Using Machine Learning by Kihoon Nam, Chanyang Park, Hyeok Yun, Jun-Sik Yoon, Hyundong Jang, Kyeongrae Cho, Min Sang Park, Hyun-Chul Choi, Rock-Hyun Baek

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