Design of module-N asynchronous counter consisting of low power double-edge-triggered D flip-flop(基于低功耗双边沿D触发器的任意进制异步计数器设计) Tekijä ZHAOMin-xiao(赵敏笑), SHUHong-fu(苏红富), CHENXie-xiong(陈偕雄)

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