An optimized algorithm for simultaneous routing and buffer insertion in multi-terminal nets by Uttraphan, C., Shaikh Husin, N.

Hybrid routing tree with buffer insertion under obstacle constraints by Uttraphan, C., Shaikh Husin, N.

Dynamic power dissipation formulation for application in dynamic programming buffer insertion algorithm by Uttraphan, C., Shaikh-Husin, N., Khalil-Hani, M.

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Algorithm to convert programmable logic controller Ladder Logic Diagram models to Petri Net models by Aspar, Z., Shaikh-Husin, N., Khalil-Hani, M.

Algorithm to convert programmable logic controller Ladder Logic Diagram models to Petri Net models by Aspar, Z., Shaikh-Husin, N., Khalil-Hani, M.

Low cost pipelined FPGA architecture of Harris Corner Detector for real-time applications by Orabi, H., Shaikh-Husin, N., Sheikh, U. U.

An optimized buffer insertion algorithm with delay-power constraints for VLSI layouts by Uttraphan, C., Shaikh Husin, N., Khalil Hani, M.

Interleaved incremental/decremental support vector machine for embedded system by Sirkunan, Jeevan, Shaikh-Husin, N., Marsono, M. N.

Hardware acceleration of a face detection system on FPGA by Dharan, S. V., Khalil-Hani, M. K. M., Shaikh-Husin, N. S.

A streaming multi-class support vector machine classification architecture for embedded systems by Sirkunan, J., Tang, J. W., Shaikh Husin, N., Marsono, M. N.

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Network partitioning and GA heuristic crossover for NOC application mapping by Tei, Y. Z., Marsono, M. N., Shaikh-Husin, N., Hau, Y. W.

Application profiling and mapping on NoC-based MPSoC emulation platform on reconfigurable logic by Tang, J. W., Hau, Y. W., Shaikh Husin, N., Marsono, M. N.

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Feasible transition path generation for EFSM-based system testing by Wong, S., Ooi, C. Y., Hau, Y. W., Marsono, M. N., Shaikh-Husin, N.

Adaptive configurable transactional memory for multi-processor FPGA platforms by Sirkunan, J., Ooi, C. Y., Shaikh-Husin, N., Hau, Y. W., Marsono, M. N.

Hardware transactional memory architecture with adaptive version management for multi-processor FPGA platforms by Sirkunan, J., Ooi, C. Y., Shaikh-Husin, N., Hau, Y. W., Marsono, M. N.

A two step binary particle swarm optimization approach for routing in VLSI by Ibrahim, Zuwairie, Zainal Abidin, Amar Faiz, Adam, Asrul, Khalil, Kamal, Ahmed Mukred, Jameel Abdulla, Abdul Salam, Mohammad Nazry, Shaikh-Husin, N., Tan, Zhe Hong, Md. Yusof, Zulkifli

A two-step binary particle swarm optimization approach for routing in VLSI with iterative RLC delay model by Md. Yusof, Zulkifli, Tan, Zhe Hong, Zainal Abidin, Amar Faiz, Abdul Salam, Mohammad Nazry, Adam, Asrul, Ahmed Mukred, Jameel Abdulla, Khalil, Kamal, Shaikh-Husin, N., Ibrahim, Zuwairie