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Progressive Multicore RLNC Decoding With Online DAG Scheduling by Simon Wunderlich, Frank H. P. Fitzek, Martin Reisslein
Published 2019-01-01
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Hardware Acceleration for RLNC: A Case Study Based on the Xtensa Processor with the Tensilica Instruction-Set Extension by Javier Acevedo, Robert Scheffel, Simon Wunderlich, Mattis Hasler, Sreekrishna Pandi, Juan Cabrera, Frank H. P. Fitzek, Gerhard Fettweis, Martin Reisslein
Published 2018-09-01
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