GPU-accelerated simulated annealing based on p-bits with real-world device-variability modeling by Naoya Onizawa, Takahiro Hanyu

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Enhanced convergence in p-bit based simulated annealing with partial deactivation for large-scale combinatorial optimization problems by Naoya Onizawa, Takahiro Hanyu

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Design of an Intermittent-Computing-Oriented Nonvolatile Register With a Switching-Probability-Aware Store-and-Verify Scheme by Masanori Natsui, Takahiro Hanyu

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Design of a nonvolatile-register-embedded RISC-V CPU with software-controlled data-retention and hardware-acceleration functions by Masanori Natsui, Keisuke Sakamoto, Takahiro Hanyu

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Local Energy Distribution Based Hyperparameter Determination for Stochastic Simulated Annealing by Naoya Onizawa, Kyo Kuroki, Duckgyu Shin, Takahiro Hanyu

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Training Hardware for Binarized Convolutional Neural Network Based on CMOS Invertible Logic by Duckgyu Shin, Naoya Onizawa, Warren J. Gross, Takahiro Hanyu

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Self-Adaptive Gate Control for Efficient Escape From Local Minimum Energy on Invertible Logic by Naoya Onizawa, Koji Yano, Seiichi Shin, Hiroyuki Fujita, Takahiro Hanyu

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Stochastic Simulated Quantum Annealing for Fast Solution of Combinatorial Optimization Problems by Naoya Onizawa, Ryoma Sasaki, Duckgyu Shin, Warren J. Gross, Takahiro Hanyu

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Sparse Random Signals for Fast Convergence on Invertible Logic by Naoya Onizawa, Makoto Kato, Hitoshi Yamagata, Koji Yano, Seiichi Shin, Hiroyuki Fujita, Takahiro Hanyu

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