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FOSS CAD for the compact Verilog-A model standardization in Open Access PDKs by Grabinski, Wladek, Scholz, Rene, Verley, Jason, Keiter, Eric R., Vogt, Holger, Warning, Dietmar, Nenzi, Paolo, Lannutti, Francesco, Salfelder, Felix, Davis, Al, Brinson, Mike, Virdee, Bal, Torri, Guilherme B., Tomaszewski, Daniel, Bucher, Matthias, Sallese, Jean-Michel, Muller, Markus, Kuthe, Pascal, Krattenmacher, Mario
Published 2024
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FOSS EKV2.6 Verilog-A Compact MOSFET Model by Brinson, Mike, Grabinski, Wladek, Pavanello, Marcelo, De Souza, Michelly, Tomaszewski, Daniel, Malesinska, Jola, Głuszko, Grzegorz, Bucher, Matthias, Makris, Nikolaos, Nikolaou, Aristeidis, Abo-Elhadid, Ahmed, Mierzwinski, Marek, Lemaitre, Laurent, Lallement, Christophe, Sallese, Jean-Michel, Yoshitomi, Sadayuki, Malisse, Paul, Oguey, Henri, Cserveny, Stefan, Enz, Christian, Krummenacher, François, Vittoz, Eric
Published 2019
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FOSS EKV2.6 at GitHub by Grabinski, Wladek, Pavanello, Marcelo, De Souza, Michelly, Tomaszewski, Daniel, Malesinska, Jola, Głuszko, Grzegorz, Bucher, Matthias, Makris, Nikolaos, Nikolaou, Aristeidis, Abo-Elhadid, Ahmed, Mierzwinski, Marek, Lemaitre, Laurent, Brinson, Mike, Lallement, Christophe, Sallese, Jean-Michel, Yoshitomi, Sadayuki, Malisse, Paul, Oguey, Henri, Cserveny, Stefan, Enz, Christian, Krummenacher, François, Vittoz, Eric
Published 2019
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