FOSS CAD for the compact Verilog-A model standardization in Open Access PDKs by Grabinski, Wladek, Scholz, Rene, Verley, Jason, Keiter, Eric R., Vogt, Holger, Warning, Dietmar, Nenzi, Paolo, Lannutti, Francesco, Salfelder, Felix, Davis, Al, Brinson, Mike, Virdee, Bal Singh, Torri, Guilherme B., Tomaszewski, Daniel, Bucher, Matthias, Sallese, Jean-Michel, Muller, Markus, Kuthe, Pascal, Krattenmacher, Mario

Get full text