Dangos 1 - 17 canlyniadau o 17 ar gyfer chwilio 'WUXun-wei(吴训威)', amser ymholiad: 0.04e Mireinio'r Canlyniadau
  1. 1
    Minimization technique of J and K excitation functions based on behaviors of flip-flop(基于触发行为的J、K激励函数的最小化技术)

    Minimization technique of J and K excitation functions based on behaviors of flip-flop(基于触发行为的J、K激励函数的最小化技术) gan WUXun-wei(吴训威), CHENHao(陈豪)

    Cyhoeddwyd 2004-03-01
    Cael y testun llawn
    Erthygl
  2. 2
    Parameters setup of AC CMOS gates(交流CMOS门电路参数的设定)

    Parameters setup of AC CMOS gates(交流CMOS门电路参数的设定) gan LIUXiao(刘晓), WUXun-wei(吴训威)

    Cyhoeddwyd 2002-05-01
    Cael y testun llawn
    Erthygl
  3. 3
    Design principle and application of double-edge-triggered shift register(双边沿移位寄存器的设计原理及其应用)

    Design principle and application of double-edge-triggered shift register(双边沿移位寄存器的设计原理及其应用) gan ZHUTing(朱挺), WUXun-wei(吴训威)

    Cyhoeddwyd 2004-01-01
    Cael y testun llawn
    Erthygl
  4. 4
    Research on short-circuit dissipation in master-slaver D flip-flop(主从型D触发器中短路功耗的研究)

    Research on short-circuit dissipation in master-slaver D flip-flop(主从型D触发器中短路功耗的研究) gan WANGLun yao(王伦耀), WUXun-wei(吴训威)

    Cyhoeddwyd 2003-07-01
    Cael y testun llawn
    Erthygl
  5. 5
    Dynamic power analysis of master-slave D flip-flop(主从型D触发器的动态功耗分析)

    Dynamic power analysis of master-slave D flip-flop(主从型D触发器的动态功耗分析) gan WANGLun-yao(王伦耀), WUXun-wei(吴训威)

    Cyhoeddwyd 2003-01-01
    Cael y testun llawn
    Erthygl
  6. 6
    Application of a current mirror in the design of multiple-valued logic I2L circuits at switch-level(电流镜及其在多值I2L电路开关级设计中的应用)

    Application of a current mirror in the design of multiple-valued logic I2L circuits at switch-level(电流镜及其在多值I2L电路开关级设计中的应用) gan WANGLun-yao(王伦耀), WUXun-wei(吴训威)

    Cyhoeddwyd 2002-07-01
    Cael y testun llawn
    Erthygl
  7. 7
    Algorithms for direct transformation of Reed-Muller expansion coefficients and spectral coefficients(Reed-Muller展开系数与谱系数之间的直接转换算法)

    Algorithms for direct transformation of Reed-Muller expansion coefficients and spectral coefficients(Reed-Muller展开系数与谱系数之间的直接转换算法) gan HANGGuo-qiang(杭国强), WUXun-wei(吴训威)

    Cyhoeddwyd 2001-03-01
    Cael y testun llawn
    Erthygl
  8. 8
    Hardware mechanism for redundancy restraint and the analysis of their working procedure(冗余抑制的硬件实现及作用过程分析)

    Hardware mechanism for redundancy restraint and the analysis of their working procedure(冗余抑制的硬件实现及作用过程分析) gan WUXun-wei(吴训威), LUYang-jian(卢仰坚)

    Cyhoeddwyd 2001-09-01
    Cael y testun llawn
    Erthygl
  9. 9
    Design of carrylook-ahead adder at switch level(超前进位全加器的开关级设计)

    Design of carrylook-ahead adder at switch level(超前进位全加器的开关级设计) gan SHENYan-fei(沈雁飞), WUXun-wei(吴训威)

    Cyhoeddwyd 2003-05-01
    Cael y testun llawn
    Erthygl
  10. 10
    Logic design of priority encoder by restraining redundancy(抑制冗余优先编码器的逻辑设计)

    Logic design of priority encoder by restraining redundancy(抑制冗余优先编码器的逻辑设计) gan LUYang-jian(卢仰坚), WUXun-wei(吴训威)

    Cyhoeddwyd 2001-07-01
    Cael y testun llawn
    Erthygl
  11. 11
    Behavior sequence and technique of generation based on multiple-valued logic(行为序列及基于多值逻辑的产生技术)

    Behavior sequence and technique of generation based on multiple-valued logic(行为序列及基于多值逻辑的产生技术) gan LUYang-jian(卢仰坚), WUXun-wei(吴训威)

    Cyhoeddwyd 2001-01-01
    Cael y testun llawn
    Erthygl
  12. 12
    Characteristics detection and generation of ternary sequences(三值序列的特征检测及其产生)

    Characteristics detection and generation of ternary sequences(三值序列的特征检测及其产生) gan WUXun-wei(吴训威), LUYang-jian(卢仰坚), XIAYin-shui(夏银水)

    Cyhoeddwyd 2001-07-01
    Cael y testun llawn
    Erthygl
  13. 13
    I2L circuits design of multiple-valued modulo-operations(多值模运算的I2L电路实现)

    I2L circuits design of multiple-valued modulo-operations(多值模运算的I2L电路实现) gan SHENGFa-sheng(盛法生), HANGGuo-qiang(杭国强), WUXun-wei(吴训威)

    Cyhoeddwyd 2002-01-01
    Cael y testun llawn
    Erthygl
  14. 14
    Design of quaternary Schmitt circuits(四值施密特电路设计)

    Design of quaternary Schmitt circuits(四值施密特电路设计) gan WANGPeng-jun(汪鹏君), SHENGFa-sheng(盛法生), WUXun-wei(吴训威)

    Cyhoeddwyd 2001-07-01
    Cael y testun llawn
    Erthygl
  15. 15
    Switch sharing of CMOS circuits in switch-level design(CMOS电路开关级设计中的开关共享研究)

    Switch sharing of CMOS circuits in switch-level design(CMOS电路开关级设计中的开关共享研究) gan WUXun-wei(吴训威), SHENYan-fei(沈雁飞), HUJian-ping(胡建平)

    Cyhoeddwyd 2002-11-01
    Cael y testun llawn
    Erthygl
  16. 16
    Low power serial magnitude comparator based on the Clock-Gating technique(基于门控技术的低功耗串行比较器)

    Low power serial magnitude comparator based on the Clock-Gating technique(基于门控技术的低功耗串行比较器) gan LUYang-jian(卢仰坚), WUXun-wei(吴训威), WangPeng-jun(汪鹏君)

    Cyhoeddwyd 2002-07-01
    Cael y testun llawn
    Erthygl
  17. 17
    A new adaptive algorithm for digital video watermarking(一种视频图像的自适应水印新算法)

    A new adaptive algorithm for digital video watermarking(一种视频图像的自适应水印新算法) gan ZHUZhong-jie(朱仲杰), JIANGGang-yi(蒋刚毅), YUMei(郁梅), WUXun-wei(吴训威)

    Cyhoeddwyd 2003-01-01
    Cael y testun llawn
    Erthygl

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