Showing 1 - 2 results of 2 for search 'Wanyuan Pan', query time: 0.02s Refine Results
  1. 1
    Design of a High-Speed, Low-Power PTL-CMOS Hybrid Multiplier Using Critical-Path Evaluation Model

    Design of a High-Speed, Low-Power PTL-CMOS Hybrid Multiplier Using Critical-Path Evaluation Model by Yihe Yu, Wanyuan Pan, Chengcheng Tang, Ningyuan Yin, Zhiyi Yu

    Published 2024-03-01
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    Article
  2. 2
    Low-Power Pass-Transistor Logic-Based Full Adder and 8-Bit Multiplier

    Low-Power Pass-Transistor Logic-Based Full Adder and 8-Bit Multiplier by Ningyuan Yin, Wanyuan Pan, Yihe Yu, Chengcheng Tang, Zhiyi Yu

    Published 2023-07-01
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    Article

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