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    A 12-bit 1.1GS/s Pipelined-SAR ADC With Adaptive Inter-Stage Redundancy in 28 nm CMOS

    A 12-bit 1.1GS/s Pipelined-SAR ADC With Adaptive Inter-Stage Redundancy in 28 nm CMOS by Xianshan Wen, Tao Fu, Liang Fang, Ping Gui

    Published 2024-01-01
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