Showing 1 - 12 results of 12 for search 'Yung-Chun, Wu', query time: 0.04s Refine Results
  1. 1
    Design and implementation of a fully digital DC servo system based on a single-chip microcomputer /

    Design and implementation of a fully digital DC servo system based on a single-chip microcomputer / by 289155 Pei-Chong, Tang, Shui-Shong, Lu, Yung-Chun, Wu

  2. 2
    Microprocessor-based design of a firing circuit for three-phase full-wave thristor dual converter /

    Microprocessor-based design of a firing circuit for three-phase full-wave thristor dual converter / by 289155 Pei-Chong, Tang, Shui-Shong, Lu, Yung-Chun, Wu

  3. 3
    Trench FinFET Nanostructure with Advanced Ferroelectric Nanomaterial HfZrO<sub>2</sub> for Sub-60-mV/Decade Subthreshold Slope for Low Power Application

    Trench FinFET Nanostructure with Advanced Ferroelectric Nanomaterial HfZrO<sub>2</sub> for Sub-60-mV/Decade Subthreshold Slope for Low Power Application by Siao-Cheng Yan, Chen-Han Wu, Chong-Jhe Sun, Yi-Wen Lin, Yi-Ju Yao, Yung-Chun Wu

    Published 2022-06-01
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  4. 4
    Threshold Voltage Adjustment by Varying Ge Content in SiGe p-Channel for Single Metal Shared Gate Complementary FET (CFET)

    Threshold Voltage Adjustment by Varying Ge Content in SiGe p-Channel for Single Metal Shared Gate Complementary FET (CFET) by Chong-Jhe Sun, Chen-Han Wu, Yi-Ju Yao, Shan-Wen Lin, Siao-Cheng Yan, Yi-Wen Lin, Yung-Chun Wu

    Published 2022-10-01
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  5. 5
    Investigation of 5-nm-Thick Hf<sub>0.5</sub>Zr<sub>0.5</sub>O<sub>2</sub> Ferroelectric FinFET Dimensions for Sub-60-mV/Decade Subthreshold Slope

    Investigation of 5-nm-Thick Hf<sub>0.5</sub>Zr<sub>0.5</sub>O<sub>2</sub> Ferroelectric FinFET Dimensions for Sub-60-mV/Decade Subthreshold Slope by Meng-Ju Tsai, Pin-Jui Chen, Dun-Bao Ruan, Fu-Ju Hou, Po-Yang Peng, Liu-Gu Chen, Yung-Chun Wu

    Published 2019-01-01
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  6. 6
    3-D Self-Aligned Stacked Ge Nanowire pGAAFET on Si nFinFET of Single Gate CFET

    3-D Self-Aligned Stacked Ge Nanowire pGAAFET on Si nFinFET of Single Gate CFET by Yi-Wen Lin, Shan-Wen Lin, Bo-An Chen, Chong-Jhe Sun, Siao-Cheng Yan, Guang-Li Luo, Yung-Chun Wu, Fu-Ju Hou

    Published 2023-01-01
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  7. 7
    Investigation of SiGe/Si Bilayer Inverted-T Channel Gate-All-Around Field-Effect-Transistor With Self-Induced Ferroelectric Ge Doped HfO&#x2082;

    Investigation of SiGe/Si Bilayer Inverted-T Channel Gate-All-Around Field-Effect-Transistor With Self-Induced Ferroelectric Ge Doped HfO&#x2082; by Chong-Jhe Sun, Yi-Ju Yao, Siao-Cheng Yan, Yi-Wen Lin, Shan-Wen Lin, Fu-Ju Hou, Guang-Li Luo, Yung-Chun Wu

    Published 2022-01-01
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  8. 8
    Silicon Heterojunction Solar Cells Using AlOx and Plasma-Immersion Ion Implantation

    Silicon Heterojunction Solar Cells Using AlOx and Plasma-Immersion Ion Implantation by Yu-Hsien Lin, Yung-Chun Wu, Hsin-Chiang You, Chun-Hao Chen, Ping-Hua Chen, Yi-He Tsai, Yi-Yun Yang, K. S. Chang-Liao

    Published 2014-06-01
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  9. 9
    Low Ge Content Ultra-Thin Fin Width (5nm) Monocrystalline SiGe n-Type FinFET With Low Off State Leakage and High I<sub>ON</sub>/I<sub>OFF</sub> Ratio

    Low Ge Content Ultra-Thin Fin Width (5nm) Monocrystalline SiGe n-Type FinFET With Low Off State Leakage and High I<sub>ON</sub>/I<sub>OFF</sub> Ratio by Chong-Jhe Sun, Meng-Ju Tsai, Siao-Cheng Yan, Tzu-Ming Chu, Chieng-Chung Hsu, Chun-Lin Chu, Guang-Li Luo, Yung-Chun Wu

    Published 2020-01-01
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  10. 10
    Fabrication and Characterization of Stacked Poly-Si Nanosheet With Gate-All-Around and Multi-Gate Junctionless Field Effect Transistors

    Fabrication and Characterization of Stacked Poly-Si Nanosheet With Gate-All-Around and Multi-Gate Junctionless Field Effect Transistors by Meng-Ju Tsai, Kang-Hui Peng, Chong-Jhe Sun, Siao-Cheng Yan, Chieng-Chung Hsu, Yu-Ru Lin, Yu-Hsien Lin, Yung-Chun Wu

    Published 2019-01-01
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  11. 11
    Low-Voltage Programmable Gate-All-Around (GAA) Nanosheet TFT Nonvolatile Memory Using Band-to-Band Tunneling Induced Hot Electron (BBHE) Method

    Low-Voltage Programmable Gate-All-Around (GAA) Nanosheet TFT Nonvolatile Memory Using Band-to-Band Tunneling Induced Hot Electron (BBHE) Method by Lun-Chun Chen, Hung-Bin Chen, Yu-Shuo Chang, Shih-Han Lin, Ming-Hung Han, Jia-Jiun Wu, Mu-Shih Yeh, Yu-Ru Lin, Yung-Chun Wu

    Published 2019-01-01
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  12. 12
    High-Performance P- and N-Type SiGe/Si Strained Super-Lattice FinFET and CMOS Inverter: Comparison of Si and SiGe FinFET

    High-Performance P- and N-Type SiGe/Si Strained Super-Lattice FinFET and CMOS Inverter: Comparison of Si and SiGe FinFET by Yi-Ju Yao, Ching-Ru Yang, Ting-Yu Tseng, Heng-Jia Chang, Tsai-Jung Lin, Guang-Li Luo, Fu-Ju Hou, Yung-Chun Wu, Kuei-Shu Chang-Liao

    Published 2023-04-01
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