Digital system emulator with design verification features [microform] /
Project Paper (Sarjana Muda Kejuruteraan (Elektrik - Elektronik)) - Universiti Teknologi Malaysia, 2006
Main Author: | Lim, Ee Wah |
---|---|
Format: | |
Language: | eng |
Published: |
Skudai : Universiti Teknologi Malaysia,
2006
|
Subjects: |
Similar Items
-
Digital system emulator with design verification features /
by: 362474 Lim, Ee Wah
Published: (2006) -
Systemverilog for verification : a guide to learning the testbench language features /
by: 402772 Spear, Chris
Published: (2008) -
SystemVerilog for verification : a guide to learning the testbench language features /
by: 402772 Spear, Chris
Published: (2006) -
Verification methodology manual for SystemVerilog /
by: Bergeron, Janick
Published: (2006) -
Digital VLSI design with verilog : a textbook from silicon valley technical institute /
by: 461186 Williams, John, et al.
Published: (2008)