Logic and architecture synthesis : proceedings of the IFIP TC10/WG10.5 Workshop on Logic and Architecture Synthesis, Paris, France, 30 May-1 June 1990 /
Includes bibliographical references.
| Main Authors: | , , |
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| Format: | |
| Language: | eng |
| Published: |
Amsterdam ; New York : North-Holland ; New York, N.Y., U.S.A. : Distributors for the U.S. and Canada, Elsevier Science Pub. Co.,
1991
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| Subjects: |
| _version_ | 1796678736118022144 |
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| author | IFIP TC10/WG10.5 Workshop on Logic and Architecture Synthesis (1990 : Paris, France) Michel, Petra Saucier, Gabriele |
| author_facet | IFIP TC10/WG10.5 Workshop on Logic and Architecture Synthesis (1990 : Paris, France) Michel, Petra Saucier, Gabriele |
| author_sort | IFIP TC10/WG10.5 Workshop on Logic and Architecture Synthesis (1990 : Paris, France) |
| collection | OCEAN |
| description | Includes bibliographical references. |
| first_indexed | 2024-03-04T20:48:45Z |
| format | |
| id | KOHA-OAI-TEST:166666 |
| institution | Universiti Teknologi Malaysia - OCEAN |
| language | eng |
| last_indexed | 2024-03-04T20:48:45Z |
| publishDate | 1991 |
| publisher | Amsterdam ; New York : North-Holland ; New York, N.Y., U.S.A. : Distributors for the U.S. and Canada, Elsevier Science Pub. Co., |
| record_format | dspace |
| spelling | KOHA-OAI-TEST:1666662020-12-19T17:04:27ZLogic and architecture synthesis : proceedings of the IFIP TC10/WG10.5 Workshop on Logic and Architecture Synthesis, Paris, France, 30 May-1 June 1990 / IFIP TC10/WG10.5 Workshop on Logic and Architecture Synthesis (1990 : Paris, France) Michel, Petra Saucier, Gabriele Amsterdam ; New York : North-Holland ; New York, N.Y., U.S.A. : Distributors for the U.S. and Canada, Elsevier Science Pub. Co.,1991.engIncludes bibliographical references.16PSZJBLIntegrated circuitsSilicon compilersURN:ISBN:0444890238 |
| spellingShingle | Integrated circuits Silicon compilers IFIP TC10/WG10.5 Workshop on Logic and Architecture Synthesis (1990 : Paris, France) Michel, Petra Saucier, Gabriele Logic and architecture synthesis : proceedings of the IFIP TC10/WG10.5 Workshop on Logic and Architecture Synthesis, Paris, France, 30 May-1 June 1990 / |
| title | Logic and architecture synthesis : proceedings of the IFIP TC10/WG10.5 Workshop on Logic and Architecture Synthesis, Paris, France, 30 May-1 June 1990 / |
| title_full | Logic and architecture synthesis : proceedings of the IFIP TC10/WG10.5 Workshop on Logic and Architecture Synthesis, Paris, France, 30 May-1 June 1990 / |
| title_fullStr | Logic and architecture synthesis : proceedings of the IFIP TC10/WG10.5 Workshop on Logic and Architecture Synthesis, Paris, France, 30 May-1 June 1990 / |
| title_full_unstemmed | Logic and architecture synthesis : proceedings of the IFIP TC10/WG10.5 Workshop on Logic and Architecture Synthesis, Paris, France, 30 May-1 June 1990 / |
| title_short | Logic and architecture synthesis : proceedings of the IFIP TC10/WG10.5 Workshop on Logic and Architecture Synthesis, Paris, France, 30 May-1 June 1990 / |
| title_sort | logic and architecture synthesis proceedings of the ifip tc10 wg10 5 workshop on logic and architecture synthesis paris france 30 may 1 june 1990 |
| topic | Integrated circuits Silicon compilers |
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