Cita APA (7a ed.)

Lim, J. J. N., Mohamed Khalil Mohd. Hani, s., & Elektrik, F. K. (2008). The RTL design of 32-BIT 5- stage pipeline risc processor using verilog HDL.

Cita Chicago Style (17a ed.)

Lim, Jonie Joo Nee, supervisor Mohamed Khalil Mohd. Hani, y Fakulti Kejuruteraan Elektrik. The RTL Design of 32-BIT 5- Stage Pipeline Risc Processor Using Verilog HDL. 2008.

Cita MLA (9a ed.)

Lim, Jonie Joo Nee, et al. The RTL Design of 32-BIT 5- Stage Pipeline Risc Processor Using Verilog HDL. 2008.