Rejab, 2. U. M. (2002). VHDL design of 32-bit parallel multiplier using the L. DADDA reduction tree method. Skudai : Universiti Teknologi Malaysia.
Dyfyniad Arddull ChicagoRejab, 274480 Uzair Md. VHDL Design of 32-bit Parallel Multiplier Using the L. DADDA Reduction Tree Method. Skudai : Universiti Teknologi Malaysia, 2002.
Dyfyniad MLARejab, 274480 Uzair Md. VHDL Design of 32-bit Parallel Multiplier Using the L. DADDA Reduction Tree Method. Skudai : Universiti Teknologi Malaysia, 2002.
Rhybudd: Mae'n bosib nad yw'r dyfyniadau hyn bob amser yn 100% cywir.