APA-viite (7. p.)

Rejab, 2. U. M. (2002). VHDL design of 32-bit parallel multiplier using the L. DADDA reduction tree method. Skudai : Universiti Teknologi Malaysia.

Chicago-viite (17. p.)

Rejab, 274480 Uzair Md. VHDL Design of 32-bit Parallel Multiplier Using the L. DADDA Reduction Tree Method. Skudai : Universiti Teknologi Malaysia, 2002.

MLA-viite (9. p.)

Rejab, 274480 Uzair Md. VHDL Design of 32-bit Parallel Multiplier Using the L. DADDA Reduction Tree Method. Skudai : Universiti Teknologi Malaysia, 2002.