VHDL design of 32-bit parallel multiplier using the L. DADDA reduction tree method /
Project Paper (Bachelor of Electrical Engineering (Electronics)) - Universiti Teknologi Malaysia, 2002
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| Формат: | |
| Мова: | eng |
| Опубліковано: |
Skudai : Universiti Teknologi Malaysia,
2002
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| Предмети: |
| _version_ | 1826402559285264384 |
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| author | 274480 Uzair Md. Rejab |
| author_facet | 274480 Uzair Md. Rejab |
| author_sort | 274480 Uzair Md. Rejab |
| collection | OCEAN |
| description | Project Paper (Bachelor of Electrical Engineering (Electronics)) - Universiti Teknologi Malaysia, 2002 |
| first_indexed | 2024-03-05T00:05:12Z |
| format | |
| id | KOHA-OAI-TEST:231903 |
| institution | Universiti Teknologi Malaysia - OCEAN |
| language | eng |
| last_indexed | 2024-03-05T00:05:12Z |
| publishDate | 2002 |
| publisher | Skudai : Universiti Teknologi Malaysia, |
| record_format | dspace |
| spelling | KOHA-OAI-TEST:2319032020-12-19T17:07:00ZVHDL design of 32-bit parallel multiplier using the L. DADDA reduction tree method / 274480 Uzair Md. Rejab Skudai : Universiti Teknologi Malaysia,2002engProject Paper (Bachelor of Electrical Engineering (Electronics)) - Universiti Teknologi Malaysia, 2002Mikrofilem negatif : MFL 11335 ra16PRZSLVHDL (Computer hardware description language)Integrated circuits |
| spellingShingle | VHDL (Computer hardware description language) Integrated circuits 274480 Uzair Md. Rejab VHDL design of 32-bit parallel multiplier using the L. DADDA reduction tree method / |
| title | VHDL design of 32-bit parallel multiplier using the L. DADDA reduction tree method / |
| title_full | VHDL design of 32-bit parallel multiplier using the L. DADDA reduction tree method / |
| title_fullStr | VHDL design of 32-bit parallel multiplier using the L. DADDA reduction tree method / |
| title_full_unstemmed | VHDL design of 32-bit parallel multiplier using the L. DADDA reduction tree method / |
| title_short | VHDL design of 32-bit parallel multiplier using the L. DADDA reduction tree method / |
| title_sort | vhdl design of 32 bit parallel multiplier using the l dadda reduction tree method |
| topic | VHDL (Computer hardware description language) Integrated circuits |
| work_keys_str_mv | AT 274480uzairmdrejab vhdldesignof32bitparallelmultiplierusingtheldaddareductiontreemethod |