Analytical threshold voltage model of nanoscale biaxial ultrathin strained-Si MOSFETs /

Analytical threshold voltage model of nanoscale biaxial ultrathin strained-Si MOSFETs /

PRZSL

Bibliographic Details
Main Authors:	Yau, Wei Heong, author, Mohammad Taghi Ahmadi, author, Razali Ismail, author, Regional Conference on Solid State Science and Technology (2009 : Pulau Pinang)
Format:
Language:
Published:	Skudai : Universiti Teknologi Malaysia, 2009

Similar Items

Impacts of ultrathin biaxial strained silicon on ultimate drive velocity, effective gate capacitance and threshold voltage /
by: Yau, Wei Heong, 1983-, et al.
Published: (2010)

Impacts of ultrathin biaxial strained silicon on ultimate drive velocity, effective gate capacitance and threshold voltage [electronic resource] /
by: Yau, Wei Heong, 1983-, et al.
Published: (2010)

Analysis of pillar thickness variation on source top (sot) nanoscale vertical mosfet with oblique rotation implatation (ORI) method /
by: Ismail Saad, author, et al.
Published: (2008)

MOSFET - like carbon nanotube field effect transistor model /
by: Mohammad Taghi Ahmadi, author, et al.
Published: (2009)

Study of breakdown in ultrathin gate dielectrics in nanoscale MOSFETs
by: Lo, Vui Lip
Published: (2010)

Channel engineering in vertical MOSFET for nanoscale /
by: Munawar Agus Riyadi, 1977-, author, et al.
Published: (2009)

Numerical study of carrier velocity for P-type strained silicon MOSFET /
by: Yau, Wei Heong, 1983-, author, et al.
Published: (2009)

The effect of different ge concentration on the characteristics of strain silicon MOSFET /
by: Razali Ismail, 1960-, author, et al.
Published: (2007)

Numerical investigation of nanoscale and vertical MOSFET incorporating dielectric pocket /
by: Zul Atfyi Fauzan Mohammed Napiah, 1983-, author, et al.
Published: (2008)

Design of soi double gate vertical mosfet /
by: Jatmiko Endro Suseno, 1972-, author, et al.
Published: (2008)

Impact of Band Nonparabolicity on Threshold Voltage of Nanoscale SOI MOSFET
by: Yasuhisa Omura
Published: (2016-01-01)

Scaling and numerical simulation analysis of 50nn MOSFET incorporating dielectric pocket (DP - MOSFET) /
by: Razali Ismail, 1960-, author, et al.
Published: (2007)

Modelling of nanoscale MOSFET using MATLAB /
by: Vijay Kumar Arora, author, et al.
Published: (2009)

Process and characterization of MOSFET incorporating dielectric pocket (DP-MOSFET) using TCAD tools /
by: Razali Ismail, 1960-, author, et al.
Published: (2007)

Simulation of post-breakdown transistor performance in ultrathin gate dielectrics-based nanoscale MOSFETs
by: Yaw, Meng Kwan.
Published: (2009)

Two-dimensional analytical threshold voltage model of nanoscale strained silicon MOSFET with tri-material gate /
by: Muhamad Syahir Tumaran, 1987-, et al.
Published: (2010)

Investigation on the effects of oblique rotating ion implantation (ORI) for nanoscale vertical double gate NMOSFET /
by: Razali Ismail, 1960-, author, et al.
Published: (2007)

Design of 100nm pMOSFET with a SiGe heterostructure channel /
by: Wong, Yah Jin, 1983-, author, et al.
Published: (2007)

The dependence of saturation velocity on temperature, inversion charge and electric field in a nanoscale MOSFET
by: Saad, Ismail, et al.
Published: (2010)

Design and characterisation of biaxial strained silicon N-channel MOSFET /
by: 521413 Lau, Ngei Ong, et al.
Published: (2010)

Extraction of SPICE model for double gate vertical MOSFET /
by: Jatmiko Endro Suseno, author, et al.
Published: (2009)

Evolution of GaAs capping layer on In0.5Gao.5As/GaAs quantum dors structure /
by: Didik Aryanto, 1983-, author, et al.
Published: (2009)

Advanced fabrication techniques for designing nanoscale mosfet /
by: 266516 Wong, Suei Huey, et al.
Published: (2007)

Modelling of nanoscale MOSFET performance in the velocity saturation region
by: Tan, Micheal Loong Peng, et al.
Published: (2007)

Numerical analysis of double gate (DG)vertical MOSFETs incorporating dielectric pocket (DP) in nanoscale regime /
by: Ismail Saad, autho, et al.
Published: (2008)

On Backscattering and Mobility in Nanoscale Silicon MOSFETs
by: Jeong, Changwook, et al.
Published: (2010)

Transport enhancement techniques for nanoscale MOSFETs
by: Khakifirooz, Ali
Published: (2008)

1/f noise in MOSFETs with ultrathin gate dielectrics
by: Gross, Blaine Jeffrey.
Published: (2005)

Device design consideration for nanoscale MOSFET using semiconductor TCAD tools
by: Teoh, Chin Hong, et al.
Published: (2006)

International conference on solid state science and technology, 18 -20 August 1992 Penang, Malaysia : abstracts /
by: International Conference on Solid State Science and Technology (1992 : Universiti Sains Malaysia, Pulau Pinang), et al.
Published: (1992)

New insights on ballistic versus scattering-limited transport in a nanoscale metal-oxide-semiconductor-field-effect-transistor /
by: Vijay Kumar Arora, author, et al.
Published: (2007)

Physics-based simulation of carrier velocity in 2-dimensional P-type MOSFET /
by: Munawar Agus Riyadi, 1977-, author, et al.
Published: (2009)

Revealing strainiinduced effects in ultrathin heterostructures at the nanoscale
by: Sarwat, S, et al.
Published: (2018)

Enhanced performance of nanoscale vertical MOSFET by oblique rotating implantation (ORI) and fillet local oxidation(FILOX+ORI)technology /
by: Ismail Saad, 1974-, author, et al.
Published: (2009)

Numerical simulation characterization of 50nm MOSFET incorporating dielectric poket (DP - MOSFET) /
by: Zul Atfyi Fauzan Mohammed Napiah, 1983-, author, et al.
Published: (2007)

Modeling the effect of velocity saturation in nanoscale mosfet /
by: 560362 Tan, Michael Loong Peng
Published: (2006)

Modeling the effect of velocity saturation in nanoscale MOSFET
by: Tan, Michael Loong Peng
Published: (2006)

Semi - empirical device model for nanoscale MOSFET /
by: 418115 Lai, Zyn Ming, et al.
Published: (2007)

27 TECHNOLOGY AND DEVICE NANOSCALE MOSFETS SIMULATION
by: T. T. Trung, et al.
Published: (2019-06-01)

Surface morphology and crystallinity of biaxially stretched PET films on the nanoscale
by: Dinelli, F, et al.
Published: (2000)