Digital computer arithmetic datapath design using verilog hdl /
16
| Main Author: | |
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| Format: | |
| Language: | eng |
| Published: |
Dordrecht : Kluwer Academic Publishers,
2004
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| Subjects: |
| _version_ | 1796701899438686208 |
|---|---|
| author | Stine, James E., 1966- |
| author_facet | Stine, James E., 1966- |
| author_sort | Stine, James E., 1966- |
| collection | OCEAN |
| description | 16 |
| first_indexed | 2024-03-05T02:20:57Z |
| format | |
| id | KOHA-OAI-TEST:277218 |
| institution | Universiti Teknologi Malaysia - OCEAN |
| language | eng |
| last_indexed | 2024-03-05T02:20:57Z |
| publishDate | 2004 |
| publisher | Dordrecht : Kluwer Academic Publishers, |
| record_format | dspace |
| spelling | KOHA-OAI-TEST:2772182020-12-19T17:08:57ZDigital computer arithmetic datapath design using verilog hdl / Stine, James E., 1966- Dordrecht : Kluwer Academic Publishers,2004eng16PSZJBLDigital electronicsVerilog (Computer hardware description language)Computer arithmeticURN:ISBN:1402077106(hbk.) |
| spellingShingle | Digital electronics Verilog (Computer hardware description language) Computer arithmetic Stine, James E., 1966- Digital computer arithmetic datapath design using verilog hdl / |
| title | Digital computer arithmetic datapath design using verilog hdl / |
| title_full | Digital computer arithmetic datapath design using verilog hdl / |
| title_fullStr | Digital computer arithmetic datapath design using verilog hdl / |
| title_full_unstemmed | Digital computer arithmetic datapath design using verilog hdl / |
| title_short | Digital computer arithmetic datapath design using verilog hdl / |
| title_sort | digital computer arithmetic datapath design using verilog hdl |
| topic | Digital electronics Verilog (Computer hardware description language) Computer arithmetic |
| work_keys_str_mv | AT stinejamese1966 digitalcomputerarithmeticdatapathdesignusingveriloghdl |