Verification methodology manual for SystemVerilog /
16
| Main Author: | |
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| Format: | |
| Language: | eng |
| Published: |
New York, NY : Springer,
2006
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| Subjects: |
| _version_ | 1826429620657848320 |
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| author | Bergeron, Janick |
| author_facet | Bergeron, Janick |
| author_sort | Bergeron, Janick |
| collection | OCEAN |
| description | 16 |
| first_indexed | 2024-03-05T06:48:19Z |
| format | |
| id | KOHA-OAI-TEST:366234 |
| institution | Universiti Teknologi Malaysia - OCEAN |
| language | eng |
| last_indexed | 2024-03-05T06:48:19Z |
| publishDate | 2006 |
| publisher | New York, NY : Springer, |
| record_format | dspace |
| spelling | KOHA-OAI-TEST:3662342020-12-19T17:12:43ZVerification methodology manual for SystemVerilog / Bergeron, Janick New York, NY : Springer,2006eng16PSZJBLVerilog (Computer hardware description language)Integrated circuitsURN:ISBN:0387255389 (hbk.) |
| spellingShingle | Verilog (Computer hardware description language) Integrated circuits Bergeron, Janick Verification methodology manual for SystemVerilog / |
| title | Verification methodology manual for SystemVerilog / |
| title_full | Verification methodology manual for SystemVerilog / |
| title_fullStr | Verification methodology manual for SystemVerilog / |
| title_full_unstemmed | Verification methodology manual for SystemVerilog / |
| title_short | Verification methodology manual for SystemVerilog / |
| title_sort | verification methodology manual for systemverilog |
| topic | Verilog (Computer hardware description language) Integrated circuits |
| work_keys_str_mv | AT bergeronjanick verificationmethodologymanualforsystemverilog |