Switch-level timing simulation of MOS VLSI circuits /

16

Bibliographic Details
Main Author: Rao, Vasant B.
Format:
Published: Boston: Kluwer Academic Pub., 1989
Subjects:
_version_ 1826432228370939904
author Rao, Vasant B.
author_facet Rao, Vasant B.
author_sort Rao, Vasant B.
collection OCEAN
description 16
first_indexed 2024-03-05T07:27:40Z
format
id KOHA-OAI-TEST:379286
institution Universiti Teknologi Malaysia - OCEAN
last_indexed 2024-03-05T07:27:40Z
publishDate 1989
publisher Boston: Kluwer Academic Pub.,
record_format dspace
spelling KOHA-OAI-TEST:3792862020-12-19T17:13:13ZSwitch-level timing simulation of MOS VLSI circuits / Rao, Vasant B. Boston: Kluwer Academic Pub.,198916PSZJBLIntegrated circuitsURN:ISBN:0898383021
spellingShingle Integrated circuits
Rao, Vasant B.
Switch-level timing simulation of MOS VLSI circuits /
title Switch-level timing simulation of MOS VLSI circuits /
title_full Switch-level timing simulation of MOS VLSI circuits /
title_fullStr Switch-level timing simulation of MOS VLSI circuits /
title_full_unstemmed Switch-level timing simulation of MOS VLSI circuits /
title_short Switch-level timing simulation of MOS VLSI circuits /
title_sort switch level timing simulation of mos vlsi circuits
topic Integrated circuits
work_keys_str_mv AT raovasantb switchleveltimingsimulationofmosvlsicircuits