Design & implementation (FPGA) of an all digital phase locked loop (ADPLL) /

Lignende værker

• Design & implementation (VLSI) of an all digital phase locked loop (ADPLL) /
  af: 226132 Chrishanton Vethanayagam
  Udgivet: (2005)
• Design of 25MHz digital phase locked loop /
  af: 171108 Ng, Sze Keat
  Udgivet: (2005)
• VLSI implementation of analog phase detector in phase-locked loop /
  af: 352558 Nooraini Naim
  Udgivet: (2006)
• Phase-locked loops & their application/
  af: Lindsey, William C., et al.
  Udgivet: (1978)
• Design of phase-locked loop circuits, with experiments/
  af: 186418 Berlin, Howard M.
  Udgivet: (1978)