The RTL design of 32-BIT 5- stage pipeline risc processor using verilog HDL [electronic resources] /
Thesis (Sarjana Kejuruteraan (Elektrik - Komputer dan Mikroelektronik)) - Universit Teknologi Malaysia, 2008
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| Language: | eng |
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2008
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| _version_ | 1826438832537468928 |
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| author | Lim, Jonie Joo Nee, 1978- Fakulti Kejuruteraan Elektrik |
| author_facet | Lim, Jonie Joo Nee, 1978- Fakulti Kejuruteraan Elektrik |
| author_sort | Lim, Jonie Joo Nee, 1978- |
| collection | OCEAN |
| description | Thesis (Sarjana Kejuruteraan (Elektrik - Komputer dan Mikroelektronik)) - Universit Teknologi Malaysia, 2008 |
| first_indexed | 2024-03-05T09:06:10Z |
| format | |
| id | KOHA-OAI-TEST:412172 |
| institution | Universiti Teknologi Malaysia - OCEAN |
| language | eng |
| last_indexed | 2024-03-05T09:06:10Z |
| publishDate | 2008 |
| record_format | dspace |
| spelling | KOHA-OAI-TEST:4121722020-12-19T17:14:23ZThe RTL design of 32-BIT 5- stage pipeline risc processor using verilog HDL [electronic resources] / Lim, Jonie Joo Nee, 1978- Fakulti Kejuruteraan Elektrik 2008engThesis (Sarjana Kejuruteraan (Elektrik - Komputer dan Mikroelektronik)) - Universit Teknologi Malaysia, 2008PSZJBLReduced instruction set computers |
| spellingShingle | Reduced instruction set computers Lim, Jonie Joo Nee, 1978- Fakulti Kejuruteraan Elektrik The RTL design of 32-BIT 5- stage pipeline risc processor using verilog HDL [electronic resources] / |
| title | The RTL design of 32-BIT 5- stage pipeline risc processor using verilog HDL [electronic resources] / |
| title_full | The RTL design of 32-BIT 5- stage pipeline risc processor using verilog HDL [electronic resources] / |
| title_fullStr | The RTL design of 32-BIT 5- stage pipeline risc processor using verilog HDL [electronic resources] / |
| title_full_unstemmed | The RTL design of 32-BIT 5- stage pipeline risc processor using verilog HDL [electronic resources] / |
| title_short | The RTL design of 32-BIT 5- stage pipeline risc processor using verilog HDL [electronic resources] / |
| title_sort | rtl design of 32 bit 5 stage pipeline risc processor using verilog hdl electronic resources |
| topic | Reduced instruction set computers |
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