P-type silicon nanowire transistor modeling and simulation /
Thesis (Sarjana Kejuruteraan (Elektrik-Elektronik dan Telekomunikasi)) - Universiti Teknologi Malaysia, 2009
Prif Awduron: | Amir Hossein Fallahpour, 1981-, Razali Ismail, supervisor, Fakulti Kejuruteraan Elektrik |
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Fformat: | |
Iaith: | eng |
Cyhoeddwyd: |
2009
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Pynciau: |
Eitemau Tebyg
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P-type silicon nanowire transistor modeling and simulation [electronic resource] /
gan: Amir Hossein Fallahpour, 1981-, et al.
Cyhoeddwyd: (2009) -
Performance evaluation of a silicon nanowire transistor /
gan: Choe, Yuet Sheng, 1986-, et al.
Cyhoeddwyd: (2009) -
Performance evaluation of a silicon nanowire transistor [electronic resource] /
gan: Choe, Yuet Sheng, 1986-
Cyhoeddwyd: (2009) -
Fabrication and simulation of P-type junctionless silicon nanowire transistor using silicon on insulator and atomic force microscope nano lithography
gan: Dehzangi, Arash
Cyhoeddwyd: (2012) -
Modeling and simulation of silicon nanowire multi-gate nanoscale transistor /
gan: Fatimah Khairiah Abd. Hamid, 1988-, et al.
Cyhoeddwyd: (2013)