System verilog RTL modeling with embedded assertions /

System verilog RTL modeling with embedded assertions /

Thesis (Sarjana Kejuruteraan (Elektrik - Komputer dan Sistem Mikroelektronik)) - Universiti Teknologi Malaysia, 2012

Bibliographic Details
Main Authors:	Chow, Chee Siang, 1984-, Muhammad Nasir Ibrahim, Fakulti Kejuruteraan Elektrik
Format:
Language:	eng
Published:	2012
Subjects:	SystemVerilog (Computer hardware description language)

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