System verilog RTL modeling with embedded assertions[electronic resource] /
Thesis (Sarjana Kejuruteraan (Elektrik - Komputer dan Sistem Mikroelektronik)) - Universiti Teknologi Malaysia, 2012
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| Language: | eng |
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2012
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| _version_ | 1826452602366197760 |
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| author | Chow, Chee Siang, 1984- Muhammad Nasir Ibrahim |
| author_facet | Chow, Chee Siang, 1984- Muhammad Nasir Ibrahim |
| author_sort | Chow, Chee Siang, 1984- |
| collection | OCEAN |
| description | Thesis (Sarjana Kejuruteraan (Elektrik - Komputer dan Sistem Mikroelektronik)) - Universiti Teknologi Malaysia, 2012 |
| first_indexed | 2024-03-05T12:26:13Z |
| format | |
| id | KOHA-OAI-TEST:478763 |
| institution | Universiti Teknologi Malaysia - OCEAN |
| language | eng |
| last_indexed | 2024-03-05T12:26:13Z |
| publishDate | 2012 |
| record_format | dspace |
| spelling | KOHA-OAI-TEST:4787632020-12-19T17:17:39ZSystem verilog RTL modeling with embedded assertions[electronic resource] / Chow, Chee Siang, 1984- Muhammad Nasir Ibrahim 2012engThesis (Sarjana Kejuruteraan (Elektrik - Komputer dan Sistem Mikroelektronik)) - Universiti Teknologi Malaysia, 2012Includes bibliographical referencesPSZJBLNEW1SystemVerilog (Computer hardware description language) |
| spellingShingle | SystemVerilog (Computer hardware description language) Chow, Chee Siang, 1984- Muhammad Nasir Ibrahim System verilog RTL modeling with embedded assertions[electronic resource] / |
| title | System verilog RTL modeling with embedded assertions[electronic resource] / |
| title_full | System verilog RTL modeling with embedded assertions[electronic resource] / |
| title_fullStr | System verilog RTL modeling with embedded assertions[electronic resource] / |
| title_full_unstemmed | System verilog RTL modeling with embedded assertions[electronic resource] / |
| title_short | System verilog RTL modeling with embedded assertions[electronic resource] / |
| title_sort | system verilog rtl modeling with embedded assertions electronic resource |
| topic | SystemVerilog (Computer hardware description language) |
| work_keys_str_mv | AT chowcheesiang1984 systemverilogrtlmodelingwithembeddedassertionselectronicresource AT muhammadnasiribrahim systemverilogrtlmodelingwithembeddedassertionselectronicresource |