An enhanced low latency network-on-chip router optimized for prototyping on field programmable gate array /

An enhanced low latency network-on-chip router optimized for prototyping on field programmable gate array /

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Bibliografiset tiedot
Päätekijät:	Alireza Monemi, 1983-, author 511782, Muhammad Nadzir Marsono, supervisor 642192, Choi Chai Yee, supervisor 654614, Fakulti Kejuruteraan Elektrik 540663
Aineistotyyppi:	text
Kieli:	eng
Julkaistu:	Johor Bahru, Johor : Universiti Teknologi Malaysia, 2016

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