16 bit counter data acquisition implementation with high speed adder design using verilog /

Bibliographic Details
Main Authors: Nimesh Kumar Rajendra Kumar, 1993-, author 614677, Suhaila Isaak, supervisor 373417, Fakulti Kejuruteraan Elektrik 540663
Format: text
Language:eng
Published: Johor Bahru, Johor : Universiti Teknologi Malaysia, 2018
Online Access:http://dms.library.utm.my:8080/vital/access/manager/Repository/vital:115231